Power distribution is a critical factor in integrated circuit design. For example, a microprocessor integrated circuit such as a system-on-a-chip (SoC) contains numerous transistors that may shift from being idle to actively switching. The sudden transition of so many transistors into an active state causes the power supply voltage to the transistors to fluctuate. If the power supply voltage drops below a minimum required value due to such a fluctuation, the system may reset or experience an error. The resistance of the power grid providing the power supply voltage is an important factor with regard to minimizing the voltage drop in response to the sudden activation of a circuit module. For example, the number of vias (via density) from the power rail to the various transistors in a circuit module may be increased compared to other modules depending upon the power demands. In addition, the width and density of the power rails may be increased. Similarly, the number of head switches coupling one power domain's rails to a main power rail may be varied depending upon a given circuit module's power needs. Finally, the number and density of decoupling capacitors supporting a given power domain's power rails may be varied also.
It is thus conventional to design an SoC to include a plurality of power-grid tiers. Each tier corresponds to a certain set of power-grid factors such as the via density, power rail width and density, head switch density, and decoupling capacitor density factors. These power-grid factors may be better appreciated with reference to a process flow for a traditional physical design (PD) of an integrated circuit as shown in FIG. 1. The process begins with a block floorplan flow step 100 that receives various inputs such as the desired netlist, the unified power format (UPF), timing constraints, multi-voltage (MV) island constraints, and pin preferences to perform a robust power-grid plan in which the logic functions for various hard macros (circuit modules) are assigned to a given power-grid tier based upon the inputs. The power-grid planning is deemed as “robust” in that a given hard macro is assigned to a corresponding power-grid tier the resulting voltage rails will thus have the same via density and other power-grid tier factors throughout the entire hard macro. With the power-grid tiers assigned, a place and route step 105 may be performed that includes conventional cell placement, clock tree synthesis, routing, and finishing (engineering change order (ECO), and design-for-manufacturing (DFM) sub-steps. The process continues with a parasitic resistance and capacitance (RC) extraction step 110 followed by a timing, noise, and power analysis 115. Finally, the design is subjected to a current*resistance (IR) drop analysis 120 that determines whether the hard macro has regions in which the power supply voltage has dropped undesirably. If the design does not satisfy the IR drop analysis, the power-grid planning step 100, place and route step 105, RC extraction step 110 and timing, noise, and power analysis step 115 are repeated as necessary to accommodate the necessary design modification through an engineering change order (ECO).
The conventional SoC design process must also satisfy density reduction and associated cost issues. It is thus quite challenging to assign the appropriate power-grid tier to a given circuit module. If the power-grid tier is too robust for the corresponding circuit module's power demands, density suffers. Conversely, if the power grid tier is insufficient, the circuit module may reset and/or malfunction due to an insufficient power supply voltage. In addition, factors such as non-linear resistance scaling, lack of on-chip resources, increased performance requirements, density, and routability complicate the design of the power-grid. For example, FIG. 2 illustrates the power supply voltage drops (IR drops) for a conventional hard macro designed according to the process flow discussed with regard to FIG. 1. In this instance, a third tier power-grid (PG3) has been selected for the entire hard macro. The design has resulted in a variety of clusters 200 of clock (CLK) drivers having large drive strength in the vicinity of the critical path, which causes undesired localized power supply voltage drops. Yet a substantial portion of the hard macro is over-served by PG3 such as a region 205, which lowers routability and increases costs.
Accordingly, there is a need in the art for improved power-grid architectures for integrated circuits.